A data communication system generally receives a data signal without an accompanying clock signal. Hence, a CDR circuit is used in the data communication system to generate the clock signal that is phase and frequency synchronized with the data signal. The CDR circuit may be implemented either with an open-loop architecture or a closed loop architecture.
A CDR circuit typically includes a phase detector, an oscillator, and a data sampler. The phase detector determines a phase difference between a phase of the clock signal and a phase of the data signal, and generates a frequency control signal based on the phase difference. The oscillator receives the frequency control signal, and generates an oscillator output. The oscillator further recovers the clock signal from the oscillator output. The data sampler receives the clock signal, and samples the data signal based on the clock signal.
Variations or ripples in the frequency control signal may cause jitter in the oscillator output, thereby, causing errors in the clock recovery, which in turn results in data read-out errors from the data signal. To control such variations or ripples, conventional CDR circuits include a charge pump and a loop filter circuit, i.e., a proportional-integral (PI) controller. The implementation of the PI controller in the CDR circuit includes combining integral and proportional paths that require components such as capacitors, and gating and flip flop circuits. Due to the aforementioned components, such CDR circuit consume substantial power at high frequencies.
The conventional CDR circuits further include on-chip resistive-capacitive (RC) filters to filter out high frequencies. While implementing the on-chip RC filters in the CDR circuits, designers have to deal with 3rd order loops, and hence, the design of the CDR circuits become complicated due to the frequency dependent 3rd order loop behaviour. Additionally, the CDR circuits may require an off-chip capacitor to maintain the stability of the loop, thus increasing design complexity of the CDR circuits.
In light of the foregoing, it would be advantageous to have a CDR circuit that will consume less power at a high frequency, maintain loop stability, provide requisite current matching characteristics, ensure reduced leakage to provide an accurate clock signal for data sampling, and overcomes the aforementioned drawbacks.